1. Field of the Invention
The embodiments disclosed herein relate to dual power supply memory arrays and, more particularly, to a dual power supply memory array having a control circuit that dynamically selects the lower of two supply voltages for bitline pre-charge operations and an associated method.
2. Description of the Related Art
Those skilled in the art will recognize that size and power scaling are key factors considered in modern integrated circuit design. One common technique for power scaling is to reduce the supply voltage. However, with memory cells, such as static random access memory (SRAM) cells, reducing the supply voltage can increase susceptibility to stability failures (i.e., memory fails). Thus, memory arrays (e.g., SRAM arrays) have been developed that incorporate two power supply rails (i.e., a first power supply rail and a second power supply rail). The first power supply rail can be configured to have a first supply voltage and the second power supply rail can be configured to have a second supply voltage that is greater than the first supply voltage. In this case, the second or higher supply voltage (e.g., a cell supply voltage (Vcs)) of the second power supply rail can be used for memory cell operations, including wordline activation, and the first or lower supply voltage (e.g., a logic supply voltage (Vdd)) of the first power supply rail can be used for all other memory array operations, including bitline pre-charging operations. Using the second or higher supply voltage for memory cell operations avoids stability fails and using the first or lower supply voltage for all other operations allows for reduced power consumption when having a high supply voltage is not critical.
Unfortunately, power supply noise may cause the values of the first and/or second supply voltages to fluctuate such that at times the first supply voltage (Vdd) used for bitline pre-charge operations is in fact greater than the second supply voltage (Vcs) used for memory cell operations. If this occurs, stability fails can occur. Currently-used solutions for avoiding such stability fails include increasing the power to the second power supply rail (Vcs) so that the first supply voltage (Vdd) will never go above it and/or adding decoupling capacitors to the memory array so that power supply noise is minimized; however, such solutions are costly in terms of power and area consumption. Therefore, there is a need in the art for a dual power supply memory array and a method of operating the array that avoids stability fails without resulting in significant power and/or area penalties.